1. Field of the Invention
This invention relates to lithographic techniques used in micromachining and the manufacture of printed circuit patterns such as those on integrated circuits (IC's), printed circuit boards and other electronic components and packaging subassemblies. In particular, this invention relates to techniques for positive photoresist treatment during photolithographic processing that provide enhancement of the ability of conventional photolithographic processes to control and achieve small feature sizes.
2. Description of the Prior Art
In conventional processes for micromachining and fabricating printed circuit patterns on printed circuit boards, IC,'s and other circuit components, a layer of a photoresist material is first formed on a silicon, dielectric, conducting or other surface layer, such as the oxide surface layer of a dielectric film. The photoresist is then exposed by white light in the desired pattern to be formed. The resist is then developed to remove the exposed portions of the resist, leaving an image of unexposed resist protecting the portions of the layer to be preserved to form the circuit.
The partially resist covered layer is then exposed to an etching process which removes those portions of the surface layer not protected by the developed resist image. The developed resist is stripped from the component, leaving the unetched surface layer in the desired pattern. The process may be repeated to build up multiple layers of circuitry, separated by layers of other materials. The minimum dimension of pattern features that may be accurately and consistently created by the photoresist process is an important parameter of the manufacturing process because it tends to control the density of component placement that may be achieved after fabrication.
The clear historical trend is toward smaller sizes for micromachining and greater and greater component and signal density. The continuing demand has therefore been for techniques for fabricating features of smaller and smaller sizes. Various approaches have been tried to achieve these smaller feature sizes, such as e-beam and x-ray lithography, but such techniques have not been widely adopted in place of conventional microlithographic techniques.
One of the main limiting problems in achieving submicron feature sizes with conventional techniques is the difficulties encountered in the control of the shape and dimensions of the developed photoresist image before and during the etching away of the exposed surface layer.
It is necessary during such subsequent processing to subject the developed photoresist image to relatively harsh conditions during processes such as plasma etch and ion implantation. The conventional technique used to enhance the ability of the photoresist pattern to withstand such harsh conditions requires the exposure of the photoresist pattern to high temperatures in order to promote cross linkage of polymers in the photoresist materials. The cross linkage of the photoresist polymers is believed to substantially improve the strength of the material and its ability to withstand harsh conditions.
However, most available photoresist materials will flow or deform at elevated temperatures, typically in the range of about 150.degree. C. The temperatures used to promote cross linkages will cause such deformation. One widely accepted technique to prevent resist flow at higher temperatures is to expose the resist pattern to deep ultraviolet radiation, known as deep UV, combined with a high temperature bake at temperatures on the order of 200.degree. C. The combined exposure to deep UV and high temperatures has successfully permitted the fabrication of circuit patterns and micromachined features utilizing relatively harsh processes without substantial changes of geometry.
Feature size is controlled having the lithographic tools available and current minimum feature sizes are the range of 0.6 to 0.8 .mu.m. What are needed, however, are improved techniques consistently yielding smaller feature sizes in the range of about 0.1 to 0.2 .mu.m.